1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a multichip package.
2. Description of the Related Art
For example, a demand for miniaturization of a package of a portable electronic device as typified by a mobile phone has been swiftly increased because of its characteristics.
Therefore, a multichip package (MCP) technology of laminating a plurality of semiconductor chips on an insulating substrate to be formed as one package is used.
In particular, when a memory chip, e.g., a random access memory (RAM) or a flash memory and a controller chip thereof are packaged based on the MCP technology, since a higher capacity of a memory is preferable, the plurality of memory chips are laminated in many cases.
Since electroconductive pads are respectively provided on a package substrate, a memory chip, and a controller chip, these members are electrically connected with each other by connecting their pads through bonding wires.
Therefore, each chip is laminated while assuring a space where wire bonding can be effected near the pad provided on each chip.
In the multichip package, since the memory chips to be laminated usually have substantially the same size, when these memory chips are simply laminated, the pad on a chip that is arranged on a lower layer side is not exposed, and wire bonding cannot be performed.
Therefore, a multichip package in which pads are provided along one or two sides of each memory chip and the chips are laminated in a zigzag pattern so that the pads on the respective chips are exposed has been proposed (see, e.g., JP-A 2004-221215 [KOKAI]).
However, when a power supply pad that supplies a power supply voltage or a ground pad that supplies a ground voltage is arranged while being biased to one side of each memory chip surface, a voltage distribution in each chip becomes non-uniform. That is because a power supply voltage and a ground voltage are supplied to a region apart from the pad of such a chip through wiring lines in each chip, an internal wiring resistance thereof is generally large, and an influence of a drop in voltage becomes larger as distanced from the pad.
Therefore, when a consumption current is increased, a reduction in the power supply voltage and an increase in the ground voltage in the region apart from the bonded pad cannot be suppressed because of the internal wiring resistance, thereby decreasing performance of each memory chip.
Further, since the plurality of memory chips are laminated while being staggered in the same direction so that a pad region of each chip is exposed, a package size becomes large in a staggering direction.